You have already learned how to create hierarchical layout with Cadence in the software labs. This is necessary to manage complex layouts that reuse common components such as basic logic gates. The same thing is also necessary for schematics, but this hasn't been covered in the labs so far. The fist section below explains how to create hierarchical schematics, which you should use for the project, later in the class. Optional: Once you know how to do this, it is possible to run HSpice simulations without ever leaving Cadence as explained below - no netlist exporting and no need to run AWaves.
Schematic Hierarchy
Consider a simple design example: a 4:1 logic multiplexer with 2 control inputs. The design is to be done by creating a 2:1 multiplexer with 1 control input, and then assembling three of them as shown below to create the 4:1 multiplexer.
A few notations have been introduced here. First, we would like to consider the four inputs to be bits of a vector D<3:0>. But more subtle is the fact that we have used a symbol to represent a multiplexer in this schematic. There are no transistors. This is exactly what we want to do in Cadence. When we design the 2:1 multiplexer, we will create a transistor schematic and a polygon layout as you are already familiar with, but we will also create a "symbol" view that looks like the symbols used above. Then, when we create higher levels of schematics, such as the 4:1 mux, we can instantiate the 2:1 schematics, the same as we would do in the layout. So the design flow is as follows:
2:1 Mux
4:1 Mux
As you can see, the design flow is repeated in the same manner for each cell in the hierarchy, and this procedure can be repeated indefinitely to create very large/complex designs. Below is shown the schematic view for the 2:1 mux in this example. Remember to set the I/O type of your pins to either input or output as appropriate, and to do "Check and Save" on your schematic before creating the symbol. Note that the VDD and VSS pins are needed for the connections to the bulk terminals of the NMOS and PMOS devices. Even though they don't appear connected in the schematic, they are connected by reference when their names were used for the "bulk node" field when instantiating the transistors. You would also have to physically make these connections in the layout. Note that we have used a very useful feature in the schematics editor. Rather than explicitly wiring control signals S and SB around, we simply create wire stubs and label them S or SB appropriately. Cadence knows that all nets with the same name are considered connected. Labels are created with keystroke "l", and you must click directly on the wire being labeled when placing the labels.
Cadence can generate the symbol view for you automatically from the schematic. In the Design menu, chose Create Cellview -> From Cellview and select symbol from schematic. It will open a dialog box asking how to position the pins in the generated symbol. You can just hit OK for now - it will put input pins on the left and output pins on the right by default, and you can edit the symbol later if you don't like it. The auto generated symbol view looks like this:
We could just keep the symbol above, but we might like to make it look like a trapezoid so that it is more recognizable when we use it in other layouts, and separate the power supply pins from the inputs. We can do this by deleting the green box and redrawing four lines in the shape of a trapezoid. All of these shapes are just for visual purposes - they have no meaning in terms of electrical design. The only part of the symbol that is really important to the design are the red squares - these are the pins, and they are where you will connect wires to when drawing schematics. You can move these around, but be careful not to delete or rename them. It is always good to perform a "Check and Save" after making edits - it will make sure that you have exactly the same pin names in the symbol and the schematic. Here is the modified symbol view:
Now we are ready to create the schematic for the 4:1 mux. Start by creating a new schematic view as usual. Then chose "instantiate", and browse for your 2:1 mux cell. Click three times in your schematic to instantiate three copies of the mux. You should have "symbol" selected as the cellview when doing this instantiation. You will then have something like this:
When creating layouts, you will usually perform a parallel task where you instantiate 3 copies of the 2:1 mux layout into the 4:1 mux layout, but this is not shown here. Next we connect the muxes according to the original schematic drawing at the top of this page:
Just as in the 2:1 mux, we need to name all of the pins. Let's consider power first. We create the typical pins called VDD and VSS, and again use the label tool (keystroke "l") to make all of the necessary power connections.
Now consider the input pins. We could just create four input pins called A, B, C, and D and connect them to the four inputs, but this starts to become cumbersome as the number of inputs grows. We would like to have a single pin designation for "Inputs 0 through 3". This is done in Cadence with bus notation. When creating your input pins, select "input" as the I/O type, but enter D<3:0> as the pin name, and place this pin in the schematic as shown.
The schematic wire connected to pin D<3:0> actually represents four wires. This is very important to remember. When you do the layout, there must actually be four physical wires drawn that correspond to the four schematic wires. Also, we only want to connect one wire to each of our 2:1 mux inputs, as they are single signal inputs. If we just wire D<3:0> to all inputs as shown below, there is no way to know which input should go to which mux. If you perform a "Check and Save", you will get warnings about this.
This ambiguity is resolved by creating labels on what we want to be single wires indicating which signal from D should be used. Again, this is done with the label command (keystroke "l"). Labeling the wires <0>, <1>, <2>, and <3> as shown below designates which signal from vector D connects to which mux. There is a shortcut for this: enter <0:3> as the label name and check the "bus expansion on" box before placing the labels, and the next four clicks place labels <0>, <1>, <2>, and <3>. We can do the same thing for the two control bits and name the pin S<1:0> as shown below, but this time use wire labels S<0> and S<1> to indicate both the bus name and the bit number at the same time. Also included is the output pin Q, and this is the complete schematic.
Now that the 4:1 schematic is done, we can do all the normal things: export the netlist for simulation, create the layout and run LVS to compare against this schematic, etc. When you export the netlist, it will actually create a netlist with all 12 transistors connected appropriately. Also, we will need a symbol view for this 4:1 mux for when we want to use it in turn in even higher levels of the schematic hierarchy. This is done the same way as for the 2:1 mux, by selecting Design->Create Cellview->From Cellview, and optionally editing the resulting symbol shapes. The result is something like this:
That is it!
Optional: Simulation within Cadence
Say we want to simulate this 4:1 mux to test it's functionality. We could export the netlist and add various voltage sources by hand as we have done so far, but this can also be done graphically within Cadence. Note that this is not required for your project, and there are many aspects of simulation within Cadence that are not explained here. If you want to do this, you are pretty much on your own to figure it all out (other than this tutorial).
The first step is to create a simulation test cell that will contain a schematic with your 4:1 mux and any voltage sources, etc., that you need for testing. These voltage sources can be found in the NCSU_Analog_Parts library, and a few of them are listed below. They are categorized into the "Voltage Sources" and "Supply Nets" categories in the NCSU library.
| vdc | Fixed voltage source for DC or AC simulation |
| vpwl | Piece-wise linear voltage source for transient simulations |
| vpulse | Pulse voltage source for repeating clock signals for transient simulations |
| gnd | Global "ground" connection |
The "gnd" symbol is particularly important. When you netlist for simulation, the "gnd" node is considered to be node number "0" in Spice. That is, all other voltages are measured relative to this node. If you don't have this, you are likely to see some very confusing results.
Here is a schematic view set up for simulation where all multiplexer inputs have fixed inputs, the control input S<1> is fixed at 0 and the control input S<0> toggles between 0 and VDD. This should cause the 4:1 mux output to toggle between 0 and VDD as inputs D<0> and D<1> are selected.
The simulation environment is started by launching Analog Environment as you have in previous labs, but starting from this new schematic view. Follow these steps to setup and launch a simulation:
When HSpice finishes, it will print some summary information in the main icfb window and finish with "Reading simulation data.... ....successful".
The easiest way to plot simulation results is with a tool called the calculator. Start it from the Analog Environment window by selecting Tools->Calculator. To plot a transient waveform, first click "VT" in the calculator for voltage transient, then click a net in your schematic, such as s<0>. You will see an expression for this net appear in the calculator:
You can then hit "plot" to see this waveform:
If you repeat the process, on say "vout", and plot again, you will see both plots in the same waveform window:
The plot window has most of the basic functionality of cursors, etc., but few extra frills.
The calculator allows you to analyze expressions very easily. For example, say you want to know 2*vout for some reason. You could just type 2*VT("/vout") and then hit plot, or you could hit "VT", click "vout", hit "enter", then hit 2, then hit "*" to perform the operation on the calculator using postfix, or reverse polish, notation. This is very useful for adding or subtracting two voltages. For example, you could click "VT", then click net "VDD" followed by net "vout", and then click "-" in the calculator. This allows you to plot VDD - vout.
There are also special functions in the calculator to help measure propagation delays, voltage peaks, integrals, etc. For example, we could measure the power consumption of this circuit. First, we must tell the simulator to record the current through the VDD power supply (voltages are all stored by default, but not currents. For large circuits, it is a good idea to turn _off_ saving of all node voltages and only explicitly save the nodes you want. This will make your simulations faster and save disk space). This is done by selecting Outputs->Choose on schematic and then clicking the terminal of the VDD power supply. It will draw a circle in your schematic indicating that current through this terminal will be saved:
Now rerun the simulation, and note that you can plot the transient current by selecting "IT" from the calculator, clicking this terminal, and clicking "plot". Note that "erplot" will erase whatever is already in the waveform window before plotting:
We can measure power two different ways. The indirect way is by integrating the power supply current. First make sure that expression for the power supply current is in the calculator, then under special functions select "iinteg" so that you have something like this:
Then you can plot the integrated current over time (you need to use a "-" sign also, because spice reports current out of a node as having a negative value):
You could use this plot to figure out the average current by dividing the integrated current (the charge) by the simulation time. A more direct way is with the average function. This can also be found in the Special Functions list or typed as shown below:
You could plot this, but that's a roundabout way to get a single number. You can also just check the "Evaluate Buffer" box to find the number directly and find out that the average current is about 11.1 uA.
