Phase 4 has been posted, and is due on Mon. May 9th at 5pm (by email to
For this week only, Tuesday's
(4-19) office hours will be held from 11am-12pm instead of the normal time.
(4-11) For this week only, Tuesday's
(4-12) lecture will be held from 2-3:30pm in 127 Dwinelle instead of the
normal time slot.
Phase 3 has been posted, and is due on Tues. Apr. 19th at 5pm (by email to
Phase 2 has been posted, and is due on Mon. Apr. 4th at 5pm (by email to
Instructions for setting up Cadence with the GPDK 45nm process we will be
using this semester have been posted in the Software
section of the website.
(3-17) There was a minor typo in the
originally posted channel files for the project. It will not have any
affect on the channel response you have measured, but please re-download
these files when you get the chance.
Project Phase 1 has been posted, and
is due on Mon. Mar. 21st at 5pm (by email to Elad).
There will be no lecture this Thurs., Mar. 10th.
For this week only, Elad's office hours will be held on Mon. from 9-10am and
on Wed. from 9-10am.
(3-6) Some clarifications have been
added to problem #2 of Homework #3 -
please be sure to take a look at the latest version posted today.
Homework #3 has been posted, and
is due on Wed. Mar. 9th at 5pm (drop box outside Elad's office).
Elad's office hours this Thurs. (3-3) will end at 11:30pm.
If you have not already done so, please email Elad with a list of who will
be in your project group.
Elad's office hours this Tues. (3-1) have been shifted to 1:30-2:30pm.
Homework #2 has been posted, and
is due on Thurs. Feb. 17th at 5pm (drop box outside Elad's office).
Elad will be out of the office on Thurs. (2-10), and so there will be no
lecture or office hours that day
Homework #1 has been posted, and
is due on Thurs. Feb. 3rd at 5pm (drop box outside Elad's office).
Elad will be traveling on Thurs. (1-27), and hence this lecture will be
made up on Mon. 1-31 from 1:30-3:00pm in 127 Dwinelle.
Due to the graduate admissions meeting, Elad's office hours on Tues.
(1-25) will be cancelled.
Description: This course focuses on the design of the signaling,
timing, and peripheral circuitry used in modern high-speed electrical
interfaces. The system-level requirements placed on these links by
their operating environment will be reviewed and used to highlight the
implications on link architecture, performance, and power consumption.
Detailed design aspects of high-speed transmitters, receivers, equalizers
(transmit, receive, linear, decision-feedback), timing generation and recovery
circuits (phase interpolators, PLLs, DLLs), and supporting sub-systems (supply
regulators, on-chip termination, adaptation) are covered. The course material will
be integrated by a final project involving circuit design for a complete
high-speed electrical interface.
Office hours: Tues. 9-10am, Thurs. 11am-12pm, 519 Cory Hall