Date: September 18th, 2009
Project member : Ji-Hoon Park
The recent advances of the CMOS RF technology paved a way to commercially viable wireless communication systems working at multi-Gbps rate. However, a design of baseband circuits for this high-speed system is facing unique challenges. Firstly, (1) minimizing the power consumption is critical especially for mobile devices because the power is proportional to the data rate. Also, (2) as the symbol rate goes up, the propagation channel shows larger delay spread, which makes it harder to equalize the channel. (3) Finally, the recovery of frequency and timing errors between a transmitter and a receiver became challenging problems.
To build a system with reduced power consumption while achieving a performance target, in addition to (1) finding power-efficient architectures and algorithms for the equalization and synchronization, we investigate (2) the power-optimal partition between the analog and digital circuits, and (3) the dynamic reconfiguration of receiver parameters. Specifically, we found an analytic expression of the receiver performance given an impulse response of the propagation channel and tried to find an optimal parameters of the mixed-signal equalizer, so that we can adjust the structure according to the channel conditions and characteristics of the signal. Also, we are working on the channel estimation and synchronization circuit structures, which can achieve its target performance with minimum power consumption.
The goal of this research is to develop a mixed-signal baseband chip to demonstrate the feasibility of this methodology and the architecture.Read more