Design of Extremely Energy-Efficient Multi-Core Processor in Nanoscale CMOS for Media Processing in Portable Devices
Many of the future applications that will drive the need for greater performance are naturally highly parallel and process massive data sets, where individual point results are of less interest than aggregate statistics or behavior. Examples include statistical machine learning, rich human-machine interfaces, and physical modeling for games and virtual worlds. In this project, the goal is to develop new highly parallel many-core architectures that exploit the attributes of these parallel, error-tolerant applications to tolerate variability in current and upcoming technologies at very low supply voltages and hence attain large gains in energy efficiency. An integrated cross-disciplinary research program is proposed–cutting across software, architecture, and circuits. Each core is designed to be a single vector-thread lane, with an independent control processor and a vector-thread execution engine, and hundreds of such lanes will be designed to fit in the area budget. Cores with similar characteristics will be identified through the pre-characterization phase and will be grouped to form clusters. Their delay and performance will be notified to control processor, so that it can perform dynamic scheduling of tasks to cores with a goal of achieving extreme energy efficiency. Additionally, hardware delay and performance monitors will be embedded in logic so that the process variability can be controlled through immediate dynamic reconfiguration. Last, SRAM arrays will be designed using a variety of write-ability, read-ability, and stability assist techniques to enable error-free operation at low supply voltages, and will feature error correction to enable dynamic characterization and reconfiguration of memory. Together, these techniques will allow the entire system to operate at each die’s own optimal energy-efficiency point, even in the face of increasing transistor variability.Read more
Brian received his B.S. in Electrical Engineering and a minor in Technology Management from the University of California, Davis in June 2010. As an undergraduate, he worked on minimizing the data retention voltage of SRAM cells and parallel implementation of MP3 decoders. Currently he is pursuing a M.S./Ph.D. at UC Berkeley and is co-advised by Professor Bora Nikolic and Professor Krste Asanovic.
His current research interests are in energy efficient processor design in deeply scaled technologies.Read more