Congratulations to Kathy Sun for receiving the 2012-2013 Warren Dere Design Award! Kathy has been an undergraduate researcher in the ComIC group since 2011, working on the Cooperative MIMO project.Read more
The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a current-commutating mixer with a single capacitor as the output load. This capacitor forms the first stage of a two stage passive switched capacitor filter that makes up the ΣΔ modulator loop filter. The switched-capacitor filter is run at radio frequencies which gives rise to a large oversampling ratio. Availability of very good switches is one of the advantages of scaling, as for a given on-resistance; the parasitic capacitance of MOS switch becomes increasingly smaller.
This receiver architecture also provides a very good platform to implement an interference cancellation scheme. First, the receiver actually captures the entire signal up to the sampling frequency, along with the desired RF signal. This means that large, potentially blocking signals are also available at the digital output, although with compromised signal-to-noise ratio. Furthermore, by default the ΣΔ modulator has a feedback path which can be placed very close to the antenna. A digital signal processor can then be used to synthesize a cancelling signal for large interferers based on the receiver digital output. This scheme would significantly reduce the dynamic-range requirement needed for the receiver.Read more
Project Member: Katerina Papadopoulou
Extreme technology scaling gives rise to variability, which becomes a major bottleneck in analog and mixed-signal circuit design. Conventional corner modeling fails to capture the complex nature of process variability, causing either yield issued or overdesign. In order to fully exploit the potentials of a new technology for high performance one must develop techniques and methodologies to accurately predict yield, using metrics defined for the specific design of interest—or, in other words using, customized corners.
This project explores a hierarchical approach to design centering. Figure 1 shows the breakdown of a design; the goal here is to use sparse regression and propagation of variance techniques in order to model the system and blocks and in order to tune the device models, respectively. This can be achieved by extracting data from sets of test structures and representative design blocks. A set of such structures for a flash A/D has been designed in 28nm bulk and FDSOI, shown in Figure 2. Completion of this project would ensure that critical analog and mixed-signal designs can be accurately centered in a single tape-out, therefore increasing yield and lowering cost.Read more
Project Members: Ruzica Jevtic, Milovan Blagojevic, Stevo Bailey
Manycore processors will require separate voltage and clock domains for each core to maximize energy efficiency. This project looks at a specific implementation of a low-power manycore processor and optimizes the energy for a given program completion time. It considers the efficiency of the DC-to-DC converter itself, as well as the supply voltage and CPU clock frequency, when finding the minimum energy point. The goal is to create an on-chip hardware block which actively minimizes the core’s energy given a known load.
The DC-to-DC converters are energy-optimized and can supply one of four possible voltage levels. Another available knob used to minimize energy is the core body bias level. With just these two knobs, numerous possible configurations exist, and choosing the one or combination of ones to minimize the core’s energy is essential. Operating along pareto-optimal energy-delay curve requires jumping between possible supply voltage levels and CPU clock periods. Once a general formula which minimizes energy for a specific load has been found, the formula must be mapped into a dedicated hardware block. This hardware block will choose operating parameters necessary to compute with minimal energy.Read more
Process: ST 65nm
Tape-out Date: November 2011
Description: This chip contains a 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.
Related publications: VLSI 2012Read more
Congratualtions to Vinayak Nagpal and Dusan Stepanovic for finishing their PhD.Read more
Congratulations to Dusan Stepanovic, who will be presenting his paper "A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS" in VLSI 2012.Read more
|Dajana Danilovic||ST Microelectronics/ISEP, France|
|Milovan Blagojevic||ST Microelectronics/ISEP, France|
Process: TSMC 65nm
Tape-out Date: December 2009
Description: This chip contains low-power equalizers and a channel estimator for a single-carrier 60GHz baseband. A transmitter, channel emulator, and noise genertor are also included in the chip as on-chip test circuitry.
Related publications: A-SSCC 2010, JSSC Nov. 2011.Read more
|Kathy Sun||2011/2012||UC Berkeley|
Congratulations to Dusan Stepanovic for receiving the 2011 Analog Devices Inc. Outstanding Student Designer Award!Read more
Congratulations to Ji-Hoon Park for receiving the James Eaton Memorial Scholarship and to Milos Jorgovanovic for his Outstanding GSI Honorable Mention this year!Read more
Project Member: Sharon Xiao
As wireless usage grows exponentially in the coming decades, cognitive radios have been proposed as a promising solution to the problem of spectrum scarcity. The proposal allows for spectrum re-use, letting unlicensed users operate on licensed bands when their primary users are absent. In such a system, spectrum sensing is necessary to identify idle bands as well as to rapidly detect the return of a primary user. In order to assure non-interference with primary user activities, a cognitive radio system must be able to reliably detect extremely weak signals down to the low and negative SNR regimes. Furthermore, spectrum sensing must be implemented with minimal power and complexity overhead to be realizable in mobile applications.
This research explores techniques for robust and low power spectrum sensing, initially focusing on the UHF DTV bands which have been approved for cognitive radio operations by the FCC. For minimum power, we propose an analog system using sub-Nyquist equivalent-time sampling and simple energy detection. To meet sensitivity requirements for weak signals, we seek out the DTV pilot tone, a narrowband feature with an SNR improvement over overall channel SNR. We can further more robustly extract the pilot from noise by adding a second, time-delayed receive path and autocorrelating the pilot.Read more
Sharon received her B.S. degree in Electrical Engineering from the University of Texas at Austin in 2009, and her M.S. degree in the same field from the University of California, Berkeley, in 2012. She is currently pursuing her Ph.D. at UC Berkeley under the guidance of Prof. Bora Nikolic.
During undergrad, she had held internships at Silicon Laboratories in Applications Engineering for Power over Ethernet, at DLInnovations in Applications Engineering for DLP technology, and at NVIDIA in hardware verification for memory interfaces. In 2012, she interned at Nokia Research Center, where she worked on configurable high-Q RF tracking filters.
Her current research interests are analog/RF front-end receiver designs, specifically spectrum sensing circuitry for cognitive radio applications.Read more
Project Member: Katerina Papadopoulou
The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-30nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020. As CMOS technology enters the deep submicron regime, variability presents a major challenge in analog and digital circuit design, resulting in significant changes in device manufacturing technology.
The focus of this research is the design of test circuits to characterize both systematic and random variability in a modern Fully Depleted Silicon on Insulator (FDSOI) process. The first testchip was taped out in FDSOI 22/16nm technology and contains an array of test structures designed in an attempt to decouple and characterize different sources of random variation. The variation analysis performed on data from these test structures, along with SRAM and capacitorless DRAM data also included in the testchip, can help optimize circuit performance, power and yield by improving the statistical model for variability and by minimizing its effects through process and design optimization.Read more
Katerina received her Diploma in Electrical and Computer Engineering from University of Patras, Greece, in 2009 and her MSc degree in Electrical Engineering from University of California, Berkeley, in 2011.
As an undergrad, she worked with the COMES Lab and conducted research on the design and implementation of reconfigurable BCH decoders for satellite applications. In 2009, she joined the Berkeley Wireless Research Center as a graduate student researcher, under the supervision of Prof. Bora Nikolic. She has since held internships in Altera, where she worked on variability characterization of high-speed transceivers, and in Kandou Bus, where she was involved with high-speed serial link design. She is currently working toward the Ph.D degree at University of California at Berkeley.
Her current research interests include characterization of variability and robust design in deeply-scaled technology nodes, and more specifically analog design centering and yield optimization.Read more
Project Member : Matthew Weiner
Low density parity check (LDPC) codes have become popular in high-performance wireless systems because of their excellent error correcting performance. LDPC codes are a type of linear block code, which is characterized by its parity check matrix H. The decoding algorithm uses soft information to iteratively decode a received message by passing messages back and forth between variable and check nodes via a routing network. Fixed decoder designs implement the decoding algorithm for a single H matrix, allowing the use of a simple routing scheme. On the other hand, flexible decoders can switch between different H matrices at the cost of a more complicated routing system. This usually limits their maximum performance and minimum power dissipation compared to fixed designs. In this project, we aim to develop a flexible serial-parallel stream architecture suitable for 60GHz baseband applications. Our goal is a throughput of over 1Gb/s for each code rate and a power dissipation of approximately 10mW, which pushes both power and performance specifications previously reported for flexible decoders. This will be achieved by (1) using a pipelined architecture that requires no large memories to store check or variable messages, (2) exploiting the structure of the matrices to increase the number of check nodes available for lower code rates using the same hardware, and (3) shortening the length of the pipeline for lower rate codes.Read more
Project member : Ji-Hoon Park
The recent advances of the CMOS RF technology paved a way to commercially viable wireless communication systems working at multi-Gbps rate. However, a design of baseband circuits for this high-speed system is facing unique challenges. Firstly, (1) minimizing the power consumption is critical especially for mobile devices because the power is proportional to the data rate. Also, (2) as the symbol rate goes up, the propagation channel shows larger delay spread, which makes it harder to equalize the channel. (3) Finally, the recovery of frequency and timing errors between a transmitter and a receiver became challenging problems.
To build a system with reduced power consumption while achieving a performance target, in addition to (1) finding power-efficient architectures and algorithms for the equalization and synchronization, we investigate (2) the power-optimal partition between the analog and digital circuits, and (3) the dynamic reconfiguration of receiver parameters. Specifically, we found an analytic expression of the receiver performance given an impulse response of the propagation channel and tried to find an optimal parameters of the mixed-signal equalizer, so that we can adjust the structure according to the channel conditions and characteristics of the signal. Also, we are working on the channel estimation and synchronization circuit structures, which can achieve its target performance with minimum power consumption.
The goal of this research is to develop a mixed-signal baseband chip to demonstrate the feasibility of this methodology and the architecture.Read more