Communications and Integrated Circuits

Posts by katerina

An old group photo

An old group photo

Here is a group photo from Spring 2013! New photo coming soon!

ISSCC 2014

ISSCC 2014

Congratulations to Matthew Weiner, who will be presenting his paper “A 1.5-6.0 Gb/s 6.2-38.1mW LDPC Decoder for 60GHz Wireless Networks in 28nm UTBB FDSOI “ in ISSCC 2014.

RF-FPGA

RF-FPGA

Project Members: Sharon Xiao, Angie Wang, Sameet Ramakrishnan, NaiChung Kuo, Bonjern Yang,  Lucas Calderin, Antonio Puglielli, Prof. Bora Nikolic, Prof. Elad Alon, Prof. Ali Niknejad, Nokia The RF FPGA project is a DARPA-sponsored effort to design, develop, implement and demonstrate a reconfigurable hardware platform that facilitates the realization of RF front-end functions for military C-Band […]

Single-chip Planetary Low-power ASIC ...

Single-chip Planetary Low-power ASIC Spectrometer with High-resolution

Project Members: Luis Esteban Hernandez, Rachel Hochman SPLASH (Single-chip Planetary Low-power ASIC Spectrometer with High-resolution) is a low power, high resolution, digital spectrometer ASIC with on-chip ADC. The ASIC will provide a compact, low power, and radiation tolerant digital polyphase filterbank for analyzing microwave thermal emission following the first downconversion in a microwave radiometer. This […]

EECS Student Awards, 2012-2013

EECS Student Awards, 2012-2013

Congratulations to Kathy Sun for receiving the 2012-2013 Warren Dere Design Award! Kathy has been an undergraduate researcher in the ComIC group since 2011, working on the Cooperative MIMO project.

Next Generation Wireless: Reconfigura...

Next Generation Wireless: Reconfigurable Direct-RF-to-Digital Sigma-Delta Converter

Project Member: Charles Wu The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a […]

Analog Design Centering in Nanoscale ...

Analog Design Centering in Nanoscale Technologies

Project Member: Katerina Papadopoulou Extreme technology scaling gives rise to variability, which becomes a major bottleneck in analog and mixed-signal circuit design. Conventional corner modeling fails to capture the complex nature of process variability, causing either yield issued or overdesign. In order to fully exploit the potentials of a new technology for high performance one […]

Energy-Delay Optimization for a Manyc...

Energy-Delay Optimization for a Manycore Processor Implemented in 28nm CMOS

Project Members: Brian Zimmer, Yunsup Lee, Jaehwa Kwak, Milovan Blagojevic, Ruzica Jevtic, Alberto Puggelli, Ben Keller, Stevo Bailey, Pi-Feng Chiu Manycore processors will require separate voltage and clock domains for each core to maximize energy efficiency. This project looks at a specific implementation of a low-power manycore processor and optimizes the energy for a given […]

2.8GS/s 44.6mW Time-Interleaved ADC

2.8GS/s 44.6mW Time-Interleaved ADC

Designer: Dusan Stepanovic Process: ST 65nm Tape-out Date: November 2011 Description: This chip contains a 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS. Related publications: VLSI 2012

Congratulations 2012 Graduates

Congratulations 2012 Graduates

Congratualtions to Vinayak Nagpal and Dusan Stepanovic for finishing their PhD.

VLSI Symposium 2012

VLSI Symposium 2012

Congratulations to Dusan Stepanovic, who will be presenting his paper "A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS" in VLSI 2012.

Academic and Industrial Visitors

Academic and Industrial Visitors

Name Affiliation Martin Cochet STMicroelectronics/IM2NP, France

60-GHz Baseband Receiver

60-GHz Baseband Receiver

Designer: Ji-Hoon Park, Brian Richards Process: TSMC 65nm Tape-out Date: December 2009 Description: This chip contains low-power equalizers and a channel estimator for a single-carrier 60GHz baseband. A transmitter, channel emulator, and noise genertor are also included in the chip as on-chip test circuitry. Related publications: A-SSCC 2010, JSSC Nov. 2011.

Undergraduate Researchers

Undergraduate Researchers

Name Year Affiliation

ADI Outstanding Student Designer

ADI Outstanding Student Designer

Congratulations to Dusan Stepanovic for receiving the 2011 Analog Devices Inc. Outstanding Student Designer Award!

Student Awards, 2011

Student Awards, 2011

Congratulations to Ji-Hoon Park for receiving the James Eaton Memorial Scholarship and to Milos Jorgovanovic for his Outstanding GSI Honorable Mention this year!

Low Power Spectrum Sensing for Cognit...

Low Power Spectrum Sensing for Cognitive Radios

Project Member: Sharon Xiao As wireless usage grows exponentially in the coming decades, cognitive radios have been proposed as a promising solution to the problem of spectrum scarcity. The proposal allows for spectrum re-use, letting unlicensed users operate on licensed bands when their primary users are absent. In such a system, spectrum sensing is necessary […]

Sharon Xiao

Sharon Xiao

Sharon received her B.S. degree in Electrical Engineering from the University of Texas at Austin in 2009, and her M.S. degree in the same field from the University of California, Berkeley, in 2012. She is currently pursuing her Ph.D. at UC Berkeley under the guidance of Prof. Bora Nikolic. During undergrad, she had held internships […]

Fully Depleted Silicon on Insulator T...

Fully Depleted Silicon on Insulator Technology Chararacterization at sub-32nm nodes

Project Member: Katerina Papadopoulou The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-30nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020. As CMOS technology enters the deep submicron regime, variability presents a major challenge in analog […]

Katerina Papadopoulou

Katerina Papadopoulou

Katerina received her Diploma in Electrical and Computer Engineering from University of Patras, Greece, in 2009 and her MSc degree in Electrical Engineering from University of California, Berkeley, in 2011. As an undergrad, she worked with the COMES Lab and conducted research on the design and implementation of reconfigurable BCH decoders for satellite applications. In 2009, […]

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Latest News

  • An old group photo - February 20, 2015

    Here is a group photo from Spring 2013! New photo coming soon!

  • ISSCC 2014 - October 25, 2013

    Congratulations to Matthew Weiner, who will be presenting his paper "A 1.5-6.0 Gb/s 6.2-38.1mW LDPC Decoder for 60GHz Wireless Networks in 28nm UTBB FDSOI " in ISSCC 2014.

  • EECS Student Awards, 2012-2013 - April 30, 2013

    Congratulations to Kathy Sun for receiving the 2012-2013 Warren Dere Design Award! Kathy has been an undergraduate researcher in the ComIC group since 2011, working on the Cooperative MIMO project.