Here is a group photo from Spring 2013! New photo coming soon!
Project Members: Sharon Xiao, Angie Wang, Sameet Ramakrishnan, NaiChung Kuo, Bonjern Yang, Lucas Calderin, Antonio Puglielli, Prof. Bora Nikolic, Prof. Elad Alon, Prof. Ali Niknejad, Nokia The RF FPGA project is a DARPA-sponsored effort to design, develop, implement and demonstrate a reconfigurable hardware platform that facilitates the realization of RF front-end functions for military C-Band […]
Project Members: Luis Esteban Hernandez, Rachel Hochman SPLASH (Single-chip Planetary Low-power ASIC Spectrometer with High-resolution) is a low power, high resolution, digital spectrometer ASIC with on-chip ADC. The ASIC will provide a compact, low power, and radiation tolerant digital polyphase filterbank for analyzing microwave thermal emission following the first downconversion in a microwave radiometer. This […]
Project Member: Charles Wu The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a […]
Project Member: Katerina Papadopoulou Extreme technology scaling gives rise to variability, which becomes a major bottleneck in analog and mixed-signal circuit design. Conventional corner modeling fails to capture the complex nature of process variability, causing either yield issued or overdesign. In order to fully exploit the potentials of a new technology for high performance one […]
Project Members: Brian Zimmer, Yunsup Lee, Jaehwa Kwak, Milovan Blagojevic, Ruzica Jevtic, Alberto Puggelli, Ben Keller, Stevo Bailey, Pi-Feng Chiu Manycore processors will require separate voltage and clock domains for each core to maximize energy efficiency. This project looks at a specific implementation of a low-power manycore processor and optimizes the energy for a given […]
Designer: Ji-Hoon Park, Brian Richards Process: TSMC 65nm Tape-out Date: December 2009 Description: This chip contains low-power equalizers and a channel estimator for a single-carrier 60GHz baseband. A transmitter, channel emulator, and noise genertor are also included in the chip as on-chip test circuitry. Related publications: A-SSCC 2010, JSSC Nov. 2011.
Project Member: Sharon Xiao As wireless usage grows exponentially in the coming decades, cognitive radios have been proposed as a promising solution to the problem of spectrum scarcity. The proposal allows for spectrum re-use, letting unlicensed users operate on licensed bands when their primary users are absent. In such a system, spectrum sensing is necessary […]
Sharon received her B.S. degree in Electrical Engineering from the University of Texas at Austin in 2009, and her M.S. degree in the same field from the University of California, Berkeley, in 2012. She is currently pursuing her Ph.D. at UC Berkeley under the guidance of Prof. Bora Nikolic. During undergrad, she had held internships […]
Project Member: Katerina Papadopoulou The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-30nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020. As CMOS technology enters the deep submicron regime, variability presents a major challenge in analog […]
Katerina received her Diploma in Electrical and Computer Engineering from University of Patras, Greece, in 2009 and her MSc degree in Electrical Engineering from University of California, Berkeley, in 2011. As an undergrad, she worked with the COMES Lab and conducted research on the design and implementation of reconfigurable BCH decoders for satellite applications. In 2009, […]