Seng Oon Toh has won the 2011 ISSCC/DAC Student Design Contest for his entry titled "SRAM Dynamic Stability Characterization Using Pulsed Word-lines in 45nm CMOS."
Process: ST 45nm
Tape-out Date: June 2008
Description: This testchip contains circuits for characterizing variability of three different SRAM bitcells using large-scale SRAM arrays as wel as padded-out SRAM macros. It also contains variable length ring-oscillators for characterizing the impact of gate stacks and datapath length on variability.Read more
Our group presented two papers at the VLSI Circuits Symposium held in Honolulu Hawaii. They are titled: "A 1–190MSample/s 8–64 Tap Energy-Efficient Reconfigurable FIR Filter for Multi-Mode Wireless Communication," and "Dynamic SRAM stability characterization in 45nm CMOS." Congratulations to the authors!Read more
Dr. Yasumasa Tsukamoto, a distinguished SRAM designer visiting from Renesas Technology, published a paper at the 2010 International Reliability Physics Symposium on "Analysis of the Relationship between Random Telegraph Signal and Negative Bias Temperature Instability." This work was done in collaboration with Seng Oon Toh, Changhwan Shin, Andrew Mairena, Prof. Tsu-Jae King Liu, and Prof. Borivoje Nikolic.Read more
A paper from our group, titled "SRAM Stability Characterization using Tunable Ring Oscillators in 45nm CMOS," by Jason Tsai, Seng Oon Toh, Zheng Guo, Liang-Teck Pang, Prof. Tsu-Jae King Liu, and Prof. Borivoje Nikolic was published at ISSCC 2010.Read more
Seng Toh received his B.S. degree in Computer Engineering from Georgia Institute of Technology in 2002 and his M.S. degree from U.C. Berkeley in 2008. He is currently advised by Professor Nikolic and is working on his Ph. D. degree. He has held several internship positions, first at Triatek Lighting in Atlanta where he designed a building automation system. He interned at NXP semiconductors, San Jose, in 2007 where he applied power-performance optimization methodologies on a product line. More recently, he interned at AMD, Sunnyvale, where he designed a testchip for 20nm technology SRAM characterization.
His research interests are in power-performance optimization of logic circuits as well as optimization of SRAM arrays with emphasis on dynamic performance. He is a proud recipient of the IBM Ph. D. Fellowship in 2010.