High-throughput LDPC

Designer : Zhengya Zhang

Process: ST 65nm

Tape-out Date : June 2008

Description : A parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme lowers the error floor to a 10^{-14} BER. The decoder architecture is optimized for area, power, and high throughput. The resulting 5.35 mm^{2}, 65nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput while dissipating 144 mW of power.

Related Publications  : VLSI09

Design of high-throughput LDPC decoders

Project Members: Zhengya Zhang, Pamela Lee, Lara Dolecek (MIT), Professors Borivoje Nikolic, Venkat Anantharam, Martin Wainwright

Funding Sources: National Science Foundation, Marvell Semiconductor, Intel Corporation, Infineon Technologies, UC MICRO

Low-density parity-check (LDPC) codes have been demonstrated to perform very close to the Shannon limit when decoded iteratively. Sometimes excellent performance is only observed up until a moderate bit error rate (BER); at a lower BER, the error curve often changes its slope, manifesting a so-called error floor. Such error floors are a major factor in limiting the deployment of LDPC codes in high-throughput applications.

We design a parallel-serial architecture to map the decoders of structured LDPC codes to a hardware emulation platform. Experiments in the low BER region provide statistics of the error traces, which are used to investigate the causes of the error floors [1]. Different classes of errors cause error floors. But even with an optimal implementation, the error floors are inevitable due to certain combinatorial structures of the LDPC code, termed absorbing sets [2]. The effect of absorbing sets in determining the error floor level is influenced by implementation. Conventional decoder implementations tend to induce low-weight weak absorbing sets, and, as a result, elevate the error floor. We propose alternative quantization schemes and demonstrate seemingly inferior algorithms that alleviate the effects of weak absorbing sets [3]. Furthermore, we can exploit the structure of absorbing sets with a redesigned message-passing decoder to escape such local minimum states [4]. The investigative approach and ASIC design approach are unified using a Simulink-based design flow. Rapid prototyping allows us to concurrently explore the algorithmic, architectural and implementation spaces in order to optimize the decoder design.

[1] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, M. J. Wainwright, “Investigation of error floors of structured low-density parity-check codes by hardware emulation,” in Proceedings of IEEE Global Communications Conference (GLOBECOM), San Francisco CA, November 2006.
[2] L. Dolecek, Z. Zhang, V. Anantharam, M. J. Wainwright, B. Nikolic, “Analysis of absorbing sets for array-based LDPC codes,” in Proceedings of IEEE International Conference on Communications, Glasgow UK, June 2007.
[3] Z. Zhang, L. Dolecek, M. J. Wainwright, V. Anantharam, B. Nikolic, “Quantization effects of low-density parity-check decoders,” in Proceedings of IEEE International Conference on Communications, Glasgow UK, June 2007.
[4] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, M. J. Wainwright, “Lowering LDPC error floors by postprocessing,” in Proceedings of IEEE Global Communications Conference (GLOBECOM), New Orleans LA, November 2008.

Zhengya Zhang

Zhengya Zhang received the B.A.Sc. degree in computer engineering from University of Waterloo, Canada, and the M.S. degree in electrical engineering from University of California, Berkeley. He is currently a Ph.D. candidate in electrical engineering at University of California, Berkeley, where he is a member of the Berkeley Wireless Research Center. His research interest is in the design of signal processing and computation systems which require a spectrum of optimizations from algorithm to architecture and implementation. He is the recipient of the Analog Devices Outstanding Student Designer Award and the Vodafone U.S. Foundation Fellowship for his graduate research. He has held multiple internships with Nvidia and Nortel in the past.