The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a current-commutating mixer with a single capacitor as the output load. This capacitor forms the first stage of a two stage passive switched capacitor filter that makes up the ΣΔ modulator loop filter. The switched-capacitor filter is run at radio frequencies which gives rise to a large oversampling ratio. Availability of very good switches is one of the advantages of scaling, as for a given on-resistance; the parasitic capacitance of MOS switch becomes increasingly smaller.
This receiver architecture also provides a very good platform to implement an interference cancellation scheme. First, the receiver actually captures the entire signal up to the sampling frequency, along with the desired RF signal. This means that large, potentially blocking signals are also available at the digital output, although with compromised signal-to-noise ratio. Furthermore, by default the ΣΔ modulator has a feedback path which can be placed very close to the antenna. A digital signal processor can then be used to synthesize a cancelling signal for large interferers based on the receiver digital output. This scheme would significantly reduce the dynamic-range requirement needed for the receiver.Read more
Project Member: Katerina Papadopoulou
Extreme technology scaling gives rise to variability, which becomes a major bottleneck in analog and mixed-signal circuit design. Conventional corner modeling fails to capture the complex nature of process variability, causing either yield issued or overdesign. In order to fully exploit the potentials of a new technology for high performance one must develop techniques and methodologies to accurately predict yield, using metrics defined for the specific design of interest—or, in other words using, customized corners.
This project explores a hierarchical approach to design centering. Figure 1 shows the breakdown of a design; the goal here is to use sparse regression and propagation of variance techniques in order to model the system and blocks and in order to tune the device models, respectively. This can be achieved by extracting data from sets of test structures and representative design blocks. A set of such structures for a flash A/D has been designed in 28nm bulk and FDSOI, shown in Figure 2. Completion of this project would ensure that critical analog and mixed-signal designs can be accurately centered in a single tape-out, therefore increasing yield and lowering cost.Read more
Project Members: Ruzica Jevtic, Milovan Blagojevic, Stevo Bailey
Manycore processors will require separate voltage and clock domains for each core to maximize energy efficiency. This project looks at a specific implementation of a low-power manycore processor and optimizes the energy for a given program completion time. It considers the efficiency of the DC-to-DC converter itself, as well as the supply voltage and CPU clock frequency, when finding the minimum energy point. The goal is to create an on-chip hardware block which actively minimizes the core’s energy given a known load.
The DC-to-DC converters are energy-optimized and can supply one of four possible voltage levels. Another available knob used to minimize energy is the core body bias level. With just these two knobs, numerous possible configurations exist, and choosing the one or combination of ones to minimize the core’s energy is essential. Operating along pareto-optimal energy-delay curve requires jumping between possible supply voltage levels and CPU clock periods. Once a general formula which minimizes energy for a specific load has been found, the formula must be mapped into a dedicated hardware block. This hardware block will choose operating parameters necessary to compute with minimal energy.Read more
Design of Extremely Energy-Efficient Multi-Core Processor in Nanoscale CMOS for Media Processing in Portable Devices
Many of the future applications that will drive the need for greater performance are naturally highly parallel and process massive data sets, where individual point results are of less interest than aggregate statistics or behavior. Examples include statistical machine learning, rich human-machine interfaces, and physical modeling for games and virtual worlds. In this project, the goal is to develop new highly parallel many-core architectures that exploit the attributes of these parallel, error-tolerant applications to tolerate variability in current and upcoming technologies at very low supply voltages and hence attain large gains in energy efficiency. An integrated cross-disciplinary research program is proposed–cutting across software, architecture, and circuits. Each core is designed to be a single vector-thread lane, with an independent control processor and a vector-thread execution engine, and hundreds of such lanes will be designed to fit in the area budget. Cores with similar characteristics will be identified through the pre-characterization phase and will be grouped to form clusters. Their delay and performance will be notified to control processor, so that it can perform dynamic scheduling of tasks to cores with a goal of achieving extreme energy efficiency. Additionally, hardware delay and performance monitors will be embedded in logic so that the process variability can be controlled through immediate dynamic reconfiguration. Last, SRAM arrays will be designed using a variety of write-ability, read-ability, and stability assist techniques to enable error-free operation at low supply voltages, and will feature error correction to enable dynamic characterization and reconfiguration of memory. Together, these techniques will allow the entire system to operate at each die’s own optimal energy-efficiency point, even in the face of increasing transistor variability.Read more
Cooperative relaying has been envisioned as a promising technique for improving spectral efficiency in wireless networks. One way to increase the data rate of todays dense wireless networks is by utilizing the proximity of the nearby terminals. When a wireless terminal is allowed to cooperate with the nearby wireless terminals, it can utilize this proximity gain to “borrow” the antennas from these devices and form a virtual multiple-antenna transceiver. This is the basic principle of cooperative Multiple-Input Multiple-Output (MIMO) transmission, the technique that resembles that of the standard MIMO systems found in modern wireless standards, such as Wifi 802.11n and 4G LTE.
In this project we are exploring physical-layer cooperation in the uplink scenario (mobile station to base station) from a system design perspective. The project focusses on the network configuration presented on Figure 1, with one single-antenna transmit mobile terminal (source), one multiple-antenna access point (AP) or base station (BS) (destination), and many single-antenna mobile terminals (relays) close to the source and available for physical-layer cooperation. The relays are assumed to be half-duplex, i.e. they can either be in the transmit (Tx) or the receive (Rx) mode.
We have looked into several aspects of how to design such cooperative network. First, we simulated what is the capacity gain for a different number of relays and typical channel conditions. We demonstrated around 3x increase in QMF achievable rate with up to 5 relays. Second, we looked at efficient relay scheduling (when relays should be in Tx and when in Rx mode) algorithms. We have suggested a simple local scheduling algorithm that can operate in real-time and achieve an optimal rate for small number of relays, Figure 2. Third, we are looking into relay interference issue. With other nearby relays transmitting at the same time, some amount of interference from other relays is inevitable. We have suggested an efficient algorithms that can mitigate the effect of relay interference. Lastly, we would like to show proof-of-concept with a hardware implementation of the simplified version of this cooperative network. The hardware prototype has a single source, a single relay, and a two-antenna destination. We are building the complete baseband using the National Instruments (NI) platform for design and testing of wireless communication systems. The system will run on FPGA chips and use standard radio boards supplied by NI, Figure 3.Read more
Project Member: Sharon Xiao
As wireless usage grows exponentially in the coming decades, cognitive radios have been proposed as a promising solution to the problem of spectrum scarcity. The proposal allows for spectrum re-use, letting unlicensed users operate on licensed bands when their primary users are absent. In such a system, spectrum sensing is necessary to identify idle bands as well as to rapidly detect the return of a primary user. In order to assure non-interference with primary user activities, a cognitive radio system must be able to reliably detect extremely weak signals down to the low and negative SNR regimes. Furthermore, spectrum sensing must be implemented with minimal power and complexity overhead to be realizable in mobile applications.
This research explores techniques for robust and low power spectrum sensing, initially focusing on the UHF DTV bands which have been approved for cognitive radio operations by the FCC. For minimum power, we propose an analog system using sub-Nyquist equivalent-time sampling and simple energy detection. To meet sensitivity requirements for weak signals, we seek out the DTV pilot tone, a narrowband feature with an SNR improvement over overall channel SNR. We can further more robustly extract the pilot from noise by adding a second, time-delayed receive path and autocorrelating the pilot.Read more