2.8GS/s 44.6mW Time-Interleaved ADC

Designer: Dusan Stepanovic

Process: ST 65nm

Tape-out Date: November 2011

Description: This chip contains a 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.

Related publications: VLSI 2012

Behzad Boroujerdian

Behzad will receive his undergraduate degree in Electrical Engineering and Computer science from the University of California at Berkeley in 2012.

During his undergraduate studies, he researched at the Berkeley Wireless Research Center, working on developing error correction codes with Brian Zimmer . This was achieved, utilizing python to automatically generate verilog code for both encoding and decoding part of ECC to examine different trade offs. He also currently has been working on creating a memory controller with Yunsup Lee that will be used on a chip that will get taped out in March.

Dajana Danilovic

Dajana received her B.S. and M.S. degrees in Electrical Engineering from the School of Electrical Engineering, University of Belgrade, Serbia, in 2010 and 2012.

From May 2012, she is in the CIFRE PhD program with ISEP, Paris, and STMicroelectronics. She arrived in Berkeley in August 2012 to do research under the guidance of Professor Borivoje Nikolic.

Her current research interests are in RF receivers using new UTBB FDSOI technology.

Sameet Ramakrishnan

Sameet received his undergraduate degrees in Electrical Engineering and Computer Science from the University of California, Berkeley, in 2012.

During his undergraduate studies, he researched at the Berkeley Wireless Research Center, working on the Cooperative MIMO project to demonstrate cooperation among terminals as a method for improving spectral efficiency in wireless networks. He held an internship at Glowlink Telecommunications, working on modems for satellite communications. He began his studies at UC Berkeley in the Fall of 2012, and is pursing a PhD in Electrical Engineering with the guidance Professor Bora Nikolic.

His current interests are wireless communication system design and implementation.

Milovan Blagojevic

Milovan received B.Sc. and M.Sc. degrees in Electrical Engineering from School of Electrical Engineering at University of Belgrade, Serbia, in September 2010 and January 2012, respectively. During his undergrad studies he was captain of faculty basketball team, demonstrator in laboratory for Fundamentals of Electrical Engineering, and a member of student organization EESTEC.

In fall of 2010 Milovan was on 2-month internship in Hardware-software-co-design group at Institute fur Informatik 12, Erlangen, Germany. His work was based on learning and evaluating SystemVerilog for both design and verification.

From April 2011 he was on 9 months internship at Intel Belgrade, in image processing team under ultra mobility group (UMG). Internship included research and development of HDR algorithm, and it’s optimal implementation on a specific VLIW processor.

In May 2012 he enrolled in a CIFRE PhD program that is realized in cooperation of three institutions: Berkeley Wireless Research Center, company ST Microelectronics in Crolles, France, and Institute ISEP in Paris. Currently working on Energy-Performance Optimization in modern digital systems, with emphasis on advantages of new UTBB FDSOI technology.

Enjoys traveling and photography, and all kind of sports and games.

Nicholas Sutardja

Nicholas received his undergraduate degrees in Electrical Engineering and Computer Science and Applied Mathematics from the University of California, Berkeley, in 2012.

During his undergraduate studies, he researched at the Berkeley Wireless Research Center, working on the Berkeley Analog Generator project to automate analog design, optimization, and layout. He also conducted research on an integrated switched capacitor DC-DC converter for a dynamic voltage and frequency scaled microprocessor. He held an internship at Altera Corportation, working on continuous time linear equalizers for high speed communication. He began his studies at UC Berkeley in the Fall of 2012, and is pursing a PhD in Electrical Engineering with the guidance Professor Bora Nikolic and Professor Elad Alon.

His current interests are analog/digital/time converters, power converters, RF tranceiver equalization.

60-GHz Baseband Receiver

Designer: Ji-Hoon Park, Brian Richards

Process: TSMC 65nm

Tape-out Date: December 2009

Description: This chip contains low-power equalizers and a channel estimator for a single-carrier 60GHz baseband. A transmitter, channel emulator, and noise genertor are also included in the chip as on-chip test circuitry.

Related publications: A-SSCC 2010, JSSC Nov. 2011.

Brian Richards

Brian Richards received the B.S. degree in Electrical Engineering from the California Institute of Technology in 1983, and the M.S. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 1986. From 1986, he joined the research staff at the University of California, Berkeley, where he worked on large scale digital system design projects including speech recognition, full-custom ASIC design for image processing, and the Infopad portable wireless multimedia terminal. He is a founding member of the BWRC, maintaining and continuing the development of several ASIC and FPGA system design CAD tools and related libraries.  Current projects include supporting various research efforts related to prototyping and implementing wireless and low-power systems at the Berkeley Wireless Research Center.

BWRC Publications

Unified Nonlinearity and Timing Calibration of Highly Interleaved SAR A/D Converters

Project Member: Dusan Stepanovic

First demonstrations of functional wireless communication systems operating in recently opened 60GHz frequency band use very simple modulation schemes like BPSK. An alluring way to further increase data throughput in these systems is to increase the complexity of the modulation schemes. One of the main obstacles encountered in practical implementations of such systems is the power of baseband analog-to-digital (A/D) converters.

The goal of this research is to build a power efficient A/D converter in 2-3GHz sampling frequency range with resolution of 8 effective bits. The recent resurgence of successive approximation (SAR) A/D converters has demonstrated extreme power efficiency. Although the speed of SAR converters is steadily increasing thanks to the faster transistors in new process technologies it is still far away from our target frequency range. An attractive approach to shift the efficiency of SAR converters towards higher sampling rates is to use time-interleaving of multiple channels. For ultimate power efficiency the A/D converters should operate in the thermal noise limited regime. For moderate resolution SAR converters this requires use of sub-fF capacitors, which brings up the issue of matching due to both layout effects and random fluctuations. Therefore, in addition to standard channel mismatch effects, the nonlinearities of individual channels need to be corrected. In this project we propose a novel deterministic calibration algorithm with rapid convergence that unifies the correction of channel timing, gain and offset mismatch effects and nonlinearities of individual SAR converters.

Congratulations 2008 Graduates

Congratulations to Bill Tsang, Farhana Sheikh and Liang-Teck Pang for finishing their PhD, as well as to Kenny Duong, Adam Aabed and Kevin Chao for finishing their M.S. degree.