Chips Gallery
Here is a selection of the chips that the group has done :
2.8GS/s 44.6mW Time-Interleaved ADC
Last modified on 2012-12-13 20:08:09 GMT. 0 comments. Top.
Designer: Dusan Stepanovic
Process: ST 65nm
Tape-out Date: November 2011
Description: This chip contains a 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS.
Related publications: VLSI 2012
60-GHz Baseband Receiver
Last modified on 2011-07-26 23:45:46 GMT. 0 comments. Top.
Designer: Ji-Hoon Park, Brian Richards
Process: TSMC 65nm
Tape-out Date: December 2009
Description: This chip contains low-power equalizers and a channel estimator for a single-carrier 60GHz baseband. A transmitter, channel emulator, and noise genertor are also included in the chip as on-chip test circuitry.
Related publications: A-SSCC 2010, JSSC Nov. 2011.
45nm SRAM Variability Test Chip
Last modified on 2009-09-25 04:29:07 GMT. 0 comments. Top.
Designers : Lauren Jones, Seng Oon Toh, Jason Tsai, Zheng Guo, Lynn Wang, Patrick Bennett and Kyoohyun Noh
Process : ST 45nm
Tape-out Date : December 2008
Description : The SRAM Variability test chip is being designed to exercise memory and other 45nm blocks. SRAM experiments include bitline current measurements and WL/BL sweep capability, variation sensing and compensation circuits, dynamic read and write test structures to correlate with static metrics and wordline pulse generator to correlate required pulse widths with static metrics. Other experiments include parameter specific ring oscillators to characterize layout induced variability and ring oscillators with vias to the chip surface to test carbon nanotube delays.
High-throughput LDPC
Last modified on 2009-03-13 18:57:52 GMT. 0 comments. Top.
Designer : Zhengya Zhang
Process: ST 65nm
Tape-out Date : June 2008
Description : A parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme lowers the error floor to a 10^{-14} BER. The decoder architecture is optimized for area, power, and high throughput. The resulting 5.35 mm^{2}, 65nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput while dissipating 144 mW of power.
Related Publications : VLSI09
Sigma-Delta Receiver
Last modified on 2009-02-24 02:54:32 GMT. 0 comments. Top.
Designer : Renaldi Winoto
Process: ST 90nm
Tape-out Date : July 2008
Description : This chip implements a highly reconfigurable RF receiver based on a down-converting sigma-delta A/D. An input RF signal is down-coverted to baseband using a passive mixed within a second-order sigma-delta A/D. An SNR of > 59 dB is measured accross a 4-MHz bandwidth at center frequencies ranging from 400MHz to 1.7GHz. An IIP3 of >+19dBm is measured.
45nm Testchip for Variability Characterization
Last modified on 2011-01-24 22:49:56 GMT. 0 comments. Top.
Designer: Zheng Guo, Liang-Teck Pang, Andrew Carlson, Kenneth Duong, Ji-Hoon Park, Lauren Jones
Process: ST 45nm
Tape-out Date: June 2008
Description: This testchip contains circuits for characterizing variability of three different SRAM bitcells using large-scale SRAM arrays as wel as padded-out SRAM macros. It also contains variable length ring-oscillators for characterizing the impact of gate stacks and datapath length on variability.
45nm Test Chip for Variability Investigation
Last modified on 2008-08-02 23:37:52 GMT. 0 comments. Top.
Designers : Zheng Guo, Liang-Teck Pang, Andrew Carlson, Kenneth Duong
Process : ST 45nm
Tape-out Date : january 2008
Description : Test chip to measure variability in SRAM cells in large SRAM arrays, and the impact of layout on CMOS login in 45nm technology. Contains padded-out SRAM cells in small arrays, large SRAM arrays with analog multiplexors on the bitlines, and a large ring-oscillator and leakage transistor array.
Digitally Calibrated Pipelined ADC
Last modified on 2008-08-02 23:43:00 GMT. 0 comments. Top.
Designer : Bill Tsang
Process : ST 130nm
Tape-out Date : July 2007
Description : This project investigates the possibility of enhancing ADC performance using digital signal-processing techniques. It uses a slow, but accurate, sigma-delta A/D as a reference to correct the errors from a high-speed pipelined A/D. The analog circuits, comprising of a sigma-delta A/D and a pipelined A/D has been implemented in 130nm standard digital CMOS process. The digital signal processor is implemented off-chip using an FPGA.
SVD for MIMO
Last modified on 2011-07-25 17:59:44 GMT. 0 comments. Top.
Designer: Dejan Markovic
Process: 90nm STMicroelectronics
Tapeout: 2005
Description: An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN. The chip implements a 4×4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band.
2-1 MASH Sigma-Delta A/D
Last modified on 2009-01-29 20:37:20 GMT. 0 comments. Top.
Designer : Bill Tsang
Process: ST 130nm
Tape-out Date : June 2005
Description :A 2.5Vsigma-delta modulator with 97-dB peak SFDR and 82-dB peak SNDR at 1MS/s fabricated in 130-nm standard digital CMOS process. Chip dissipates 11 mW while running at 64 MHz clock frequency
Related Publications : VLSI 2006
Mixed-Signal Maskless Lithography Chip
Last modified on 2009-02-25 20:15:29 GMT. 0 comments. Top.
Designer: David Fang
Process: 90nm STMicroelectronics
Tapeout date: 2005
Description: A parallel, 12um-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3um x 3um analog DRAM cells in a 2.5/1V 90 nm CMOS process, with an application in maskless lithography. A self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5LSB over 100ms of data hold time. A 2mm x 2mm test chip implements a mixed-signal interface with 32 DACs driving four 32 × 256 analog DRAM arrays.
64-bit Ling Adder
Last modified on 2008-08-02 22:39:54 GMT. 0 comments. Top.
Designers : Sean Kao, Radu Zlatanovici, Valentin Abramzon, Elad Alon
Process : ST 90 nm
Tape-out Date : Jan 2005
Description : 8 64-bit Domino adder cores
Related Publication : ISSCC 2006
90nm Testchip for Variability Investigation
Last modified on 2009-02-25 20:08:08 GMT. 0 comments. Top.
Designer : Liang-Teck Pang
Process : ST 90nm
Tape-out Date : Dec 2004
Description : Die photo of the 90nm testchip used to investigate the effects of layout on cmos performance. This chip contains an array of ring oscillators and off-transistors. Measurement of the ring oscillator frequencies and the off-transistor leakage currents are collected and analysed to obtain variation and spatial correlation statistics.
Related Publication : VLSI2006
Pipeline ADC
Last modified on 2009-02-25 22:34:22 GMT. 0 comments. Top.
Designer: Yun Chiu
Process: 180nm STMicroelectronics
Tapeout date: 2003.
Description: A 12MS/s, 14-bit pipeline ADC with 103dB SFDR and 75.5dB of SNDR. It features SHA-less architecture, pseudo-differential nested gain boosting amplifires, passive error averaging and amplier sharing.
LDPC Decoder
Last modified on 2009-02-25 20:02:37 GMT. 0 comments. Top.
Designer: Engling Yeo
Process: 130nm STMicroelectronics
Tapeout date: 2003.
Description: A 4092-bit low-density parity-check decoder, based on staggered decoding schedule, is implemented in a 130nm 6M CMOS technology. The rate 0.75 code is based on finitefield geometries. Serial, shift-register based architecture enables a compact decoder implementation. The chip has a 4.0mm2 core and operates at 1.1 GHz with 1.2V supply, resulting in a throughput of 1.1Gb/s per iteration.
Data Decompression for Maskless Lithography
Last modified on 2009-02-25 19:45:01 GMT. 0 comments. Top.
Designer: Ben Wild
Process: 180nm STMicroelectronics
Tapeout date: 2002
Description: The chip implements a hardware implementation of data decompression which has been compressed using Lempel-Ziv algorithm. The targetted application is in maskless lithography, where the data is compressed on the server, and decompressed near the writers.
SOVA Decoder
Last modified on 2009-02-24 15:57:30 GMT. 0 comments. Top.
Designer: Engling Yeo
Dual-Supply ALU
Last modified on 2009-02-24 06:42:49 GMT. 0 comments. Top.
Designer: Yasuhisa Shimazaki
Process: 180nm STMicroelectronics
Tape-out Date: 2001
Description: This chip demonstrates the design of a shared-well dual supply 64-bit arithmetic-logic unit (ALU). The frequency of operation was 1.14GHz at 1.8V.
‘Single-Chip Filter’
Last modified on 2009-02-24 06:33:52 GMT. 0 comments. Top.
Designer: W. Rhett Davis
Process: 250nm STMicroelectronics
Tapeout date: 2000.
Description: This was the first demonstration of the automated ‘chip-in-a-day’ design flow. The design was described in Simulink and then directly mapped into layout. The chip was a decimation filter for a sigma-delta ADC.