45nm Test Chip for Variability Investigation
Designers : Zheng Guo, Liang-Teck Pang, Andrew Carlson, Kenneth Duong
Process : ST 45nm
Tape-out Date : january 2008
Description : Test chip to measure variability in SRAM cells in large SRAM arrays, and the impact of layout on CMOS login in 45nm technology. Contains padded-out SRAM cells in small arrays, large SRAM arrays with analog multiplexors on the bitlines, and a large ring-oscillator and leakage transistor array.