45nm Testchip for Variability Characterization
Designer: Zheng Guo, Liang-Teck Pang, Andrew Carlson, Kenneth Duong, Ji-Hoon Park, Lauren Jones
Process: ST 45nm
Tape-out Date: June 2008
Description: This testchip contains circuits for characterizing variability of three different SRAM bitcells using large-scale SRAM arrays as wel as padded-out SRAM macros. It also contains variable length ring-oscillators for characterizing the impact of gate stacks and datapath length on variability.