Pipeline ADC
Designer: Yun Chiu
Process: 180nm STMicroelectronics
Tapeout date: 2003.
Description: A 12MS/s, 14-bit pipeline ADC with 103dB SFDR and 75.5dB of SNDR. It features SHA-less architecture, pseudo-differential nested gain boosting amplifires, passive error averaging and amplier sharing.
