Sigma-Delta Receiver
Designer : Renaldi Winoto
Process: ST 90nm
Tape-out Date : July 2008
Description : This chip implements a highly reconfigurable RF receiver based on a down-converting sigma-delta A/D. An input RF signal is down-coverted to baseband using a passive mixed within a second-order sigma-delta A/D. An SNR of > 59 dB is measured accross a 4-MHz bandwidth at center frequencies ranging from 400MHz to 1.7GHz. An IIP3 of >+19dBm is measured.