Fully Depleted Silicon on Insulator Technology Chararacterization at sub-32nm nodes
Project Member: Katerina Papadopoulou
The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-30nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020. As CMOS technology enters the deep submicron regime, variability presents a major challenge in analog and digital circuit design, resulting in significant changes in device manufacturing technology.
The focus of this research is the design of test circuits to characterize both systematic and random variability in a modern Fully Depleted Silicon on Insulator (FDSOI) process. The first testchip was taped out in FDSOI 22/16nm technology and contains an array of test structures designed in an attempt to decouple and characterize different sources of random variation. The variation analysis performed on data from these test structures, along with SRAM and capacitorless DRAM data also included in the testchip, can help optimize circuit performance, power and yield by improving the statistical model for variability and by minimizing its effects through process and design optimization.