Sigma-Delta Receiver

Project Member : Renaldi Winoto

The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a current-commutating mixer with a single capacitor as the output load. This capacitor forms the first stage of a two stage passive switched capacitor filter that makes up the ΣΔ modulator loop filter. The switched-capacitor filter is run at radio frequencies which gives rise to a large oversampling ratio. Availability of very good switches is one of the advantages of scaling, as for a given on-resistance; the parasitic capacitance of MOS switch becomes increasingly smaller.

 

This receiver architecture also provides a very good platform to implement an interference cancellation scheme. First, the receiver actually captures the entire signal up to the sampling frequency, along with the desired RF signal. This means that large, potentially blocking signals are also available at the digital output, although with compromised signal-to-noise ratio. Furthermore, by default the ΣΔ modulator has a feedback path which can be placed very close to the antenna. A digital signal processor can then be used to synthesize a cancelling signal for large interferers based on the receiver digital output. This scheme would significantly reduce the dynamic-range requirement needed for the receiver.