VLSI Technology Exploration
Project Member: Katerina Papadopoulou
Extreme technology scaling gives rise to variability, which becomes a major bottleneck in analog and mixed-signal circuit design. Conventional corner modeling fails to capture the complex nature of process variability, causing either yield issued or overdesign. In order to fully exploit the potentials of a new technology for high performance one must develop techniques and methodologies to accurately predict yield, using metrics defined for the specific design of interest—or, in other words using, customized corners.
This project explores a hierarchical approach to design centering. Figure 1 shows the breakdown of a design; the goal here is to use sparse regression and propagation of variance techniques in order to model the system and blocks and in order to tune the device models, respectively. This can be achieved by extracting data from sets of test structures and representative design blocks. A set of such structures for a flash A/D has been designed in 28nm bulk and FDSOI, shown in Figure 2. Completion of this project would ensure that critical analog and mixed-signal designs can be accurately centered in a single tape-out, therefore increasing yield and lowering cost.
Project Members: Ruzica Jevtic, Milovan Blagojevic, Stevo Bailey
Manycore processors will require separate voltage and clock domains for each core to maximize energy efficiency. This project looks at a specific implementation of a low-power manycore processor and optimizes the energy for a given program completion time. It considers the efficiency of the DC-to-DC converter itself, as well as the supply voltage and CPU clock frequency, when finding the minimum energy point. The goal is to create an on-chip hardware block which actively minimizes the core’s energy given a known load.
The DC-to-DC converters are energy-optimized and can supply one of four possible voltage levels. Another available knob used to minimize energy is the core body bias level. With just these two knobs, numerous possible configurations exist, and choosing the one or combination of ones to minimize the core’s energy is essential. Operating along pareto-optimal energy-delay curve requires jumping between possible supply voltage levels and CPU clock periods. Once a general formula which minimizes energy for a specific load has been found, the formula must be mapped into a dedicated hardware block. This hardware block will choose operating parameters necessary to compute with minimal energy.
Design of Extremely Energy-Efficient Multi-Core Processor in Nanoscale CMOS for Media Processing in Portable Devices
Many of the future applications that will drive the need for greater performance are naturally highly parallel and process massive data sets, where individual point results are of less interest than aggregate statistics or behavior. Examples include statistical machine learning, rich human-machine interfaces, and physical modeling for games and virtual worlds. In this project, the goal is to develop new highly parallel many-core architectures that exploit the attributes of these parallel, error-tolerant applications to tolerate variability in current and upcoming technologies at very low supply voltages and hence attain large gains in energy efficiency. An integrated cross-disciplinary research program is proposed–cutting across software, architecture, and circuits. Each core is designed to be a single vector-thread lane, with an independent control processor and a vector-thread execution engine, and hundreds of such lanes will be designed to fit in the area budget. Cores with similar characteristics will be identified through the pre-characterization phase and will be grouped to form clusters. Their delay and performance will be notified to control processor, so that it can perform dynamic scheduling of tasks to cores with a goal of achieving extreme energy efficiency. Additionally, hardware delay and performance monitors will be embedded in logic so that the process variability can be controlled through immediate dynamic reconfiguration. Last, SRAM arrays will be designed using a variety of write-ability, read-ability, and stability assist techniques to enable error-free operation at low supply voltages, and will feature error correction to enable dynamic characterization and reconfiguration of memory. Together, these techniques will allow the entire system to operate at each die’s own optimal energy-efficiency point, even in the face of increasing transistor variability.