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	<title>Digital Circuit Design Group</title>
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	<link>http://bwrcs.eecs.berkeley.edu/dcdg</link>
	<description>Berkeley Wireless Research Center</description>
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		<title>Design of Flexible High-Throughput, Low-Power LDPC Decoders</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/design-of-flexible-high-throughput-low-power-ldpc-decoders-2/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/design-of-flexible-high-throughput-low-power-ldpc-decoders-2/#comments</comments>
		<pubDate>Sat, 10 Oct 2009 23:25:13 +0000</pubDate>
		<dc:creator>katerina</dc:creator>
				<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=518</guid>
		<description><![CDATA[Project Member : Matthew Weiner
Low density parity check (LDPC) codes have become popular in high-performance wireless systems because of their excellent error correcting performance. LDPC codes are a type of linear block code, which is characterized by its parity check matrix H. The decoding algorithm uses soft information to iteratively decode a received message by [...]]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/design-of-flexible-high-throughput-low-power-ldpc-decoders-2/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>IEDM 2009 Conference</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/news/iedm-2009-conference/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/news/iedm-2009-conference/#comments</comments>
		<pubDate>Tue, 22 Sep 2009 16:57:05 +0000</pubDate>
		<dc:creator>sengoon</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=493</guid>
		<description><![CDATA[A paper from our group, titled &#8220;Impact of Random Telegraph Signals on Vmin in 45nm SRAM,&#8221; authored by Seng Oon Toh, Yasumasa Tsukamoto, Zheng Guo, Lauren Jones, Tsu-Jae King Liu, and Borivoje Nikolic has been accepted for presentation at the 2009 International Electron Devices Meeting (IEDM). The paper will be presented in Baltimore, Maryland on [...]]]></description>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>A Baseband Design for a High-Speed Wireless Receiver</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/a-baseband-design-for-a-high-speed-wireless-receiver/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/a-baseband-design-for-a-high-speed-wireless-receiver/#comments</comments>
		<pubDate>Fri, 18 Sep 2009 23:04:42 +0000</pubDate>
		<dc:creator>katerina</dc:creator>
				<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=483</guid>
		<description><![CDATA[Project member : Ji-Hoon Park
The recent advances of the CMOS RF technology paved a way to commercially viable wireless communication systems working at multi-Gbps rate. However, a design of baseband circuits for this high-speed system is facing unique challenges. Firstly, (1) minimizing the power consumption is critical especially for mobile devices because the power is proportional to [...]]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/a-baseband-design-for-a-high-speed-wireless-receiver/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>ISSCC/DAC Student Design Contest</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/issccdac-student-design-contest/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/issccdac-student-design-contest/#comments</comments>
		<pubDate>Fri, 08 May 2009 18:52:15 +0000</pubDate>
		<dc:creator>bora</dc:creator>
				<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=456</guid>
		<description><![CDATA[Zheng Guo, Drew Carlson, Liang-Teck Pang and Kenny Duong have won the 2009 ISSCC/DAC Student Design Contest!
]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/uncategorized/issccdac-student-design-contest/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>Student Awards</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/news/student-awards/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/news/student-awards/#comments</comments>
		<pubDate>Fri, 08 May 2009 18:50:21 +0000</pubDate>
		<dc:creator>bora</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=453</guid>
		<description><![CDATA[Two major awards for our group this May:
Zhengya Zhang has won the David J. Sakrison Memorial Award for 2009 which is made &#8221;to a graduate student who has completed what is deemed by a faculty committee to be a truly outstanding piece of research.&#8221;  This is the second Sakrison Award for our group in three years!
Renaldi [...]]]></description>
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		<slash:comments>0</slash:comments>
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		<title>45nm SRAM Variability Test Chip</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/chips/45nm-sram-variability-test-chip/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/chips/45nm-sram-variability-test-chip/#comments</comments>
		<pubDate>Fri, 24 Apr 2009 18:57:42 +0000</pubDate>
		<dc:creator>ljones03</dc:creator>
				<category><![CDATA[Chips]]></category>
		<category><![CDATA[SRAM]]></category>
		<category><![CDATA[Variability]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=450</guid>
		<description><![CDATA[Designers : Lauren Jones, Seng Oon Toh, Jason Tsai, Zheng Guo, Lynn Wang, Patrick Bennett and Kyoohyun Noh
Process : ST 45nm
Tape-out Date : December 2008
Description : The SRAM Variability test chip is being designed to exercise memory and other 45nm blocks.  SRAM experiments include bitline current measurements and WL/BL sweep capability, variation sensing and [...]]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/chips/45nm-sram-variability-test-chip/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Bastien Giraud</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/people/bastien-giraud/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/people/bastien-giraud/#comments</comments>
		<pubDate>Thu, 19 Mar 2009 22:03:03 +0000</pubDate>
		<dc:creator>bgiraud</dc:creator>
				<category><![CDATA[Current]]></category>
		<category><![CDATA[People]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=434</guid>
		<description><![CDATA[

Bastien Giraud received his Engineer’s degree in Computer Engineering, Electronics and Telecommunications from Institut Supérieur d’Electronique et du Numérique (ISEN, France) and his Master degree in Microelectronics at Polytechnique Marseille (France) in 2005. His major field concerns advanced circuit design. In 2005, he spent 5-months master thesis at Interuniversity MicroElectronics Center (IMEC, Belgium) where he [...]]]></description>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>VLSI 2009 Conference</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/news/vlsi-2009-conference/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/news/vlsi-2009-conference/#comments</comments>
		<pubDate>Thu, 19 Mar 2009 18:13:56 +0000</pubDate>
		<dc:creator>Renaldi</dc:creator>
				<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=427</guid>
		<description><![CDATA[Two papers from our group by Renaldi Winoto and Zhengya Zhang have been accepted for publication at the 2009 VLSI Circuits Symposium. The papers will be presented in Kyoto, Japan on June 17th and 18th. The two papers are available here and here.
]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/news/vlsi-2009-conference/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>High-throughput LDPC</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/chips/high-throughput-ldpc/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/chips/high-throughput-ldpc/#comments</comments>
		<pubDate>Fri, 13 Mar 2009 18:50:48 +0000</pubDate>
		<dc:creator>zyzhang</dc:creator>
				<category><![CDATA[Chips]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=417</guid>
		<description><![CDATA[Designer : Zhengya Zhang
Process: ST 65nm
Tape-out Date : June 2008
Description : A parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme lowers the error floor to a 10^{-14} BER. The decoder architecture is optimized for area, power, and high throughput. The resulting [...]]]></description>
		<wfw:commentRss>http://bwrcs.eecs.berkeley.edu/dcdg/chips/high-throughput-ldpc/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>SVD for MIMO</title>
		<link>http://bwrcs.eecs.berkeley.edu/dcdg/chips/svd-for-mimo/</link>
		<comments>http://bwrcs.eecs.berkeley.edu/dcdg/chips/svd-for-mimo/#comments</comments>
		<pubDate>Wed, 25 Feb 2009 20:21:02 +0000</pubDate>
		<dc:creator>bora</dc:creator>
				<category><![CDATA[Chips]]></category>

		<guid isPermaLink="false">http://bwrcs.eecs.berkeley.edu/dcdg/?p=392</guid>
		<description><![CDATA[Designer: Dejan Markovic
Process: 90nm STMicroelectronics
Tapeout: 2005
Description: An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN. The chip implements a 4x4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented [...]]]></description>
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		<slash:comments>0</slash:comments>
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