Integrated Circuits for Wireless Communication Systems
A Baseband Design for a High-Speed Wireless Receiver
Last modified on 2009-09-18 23:04:42 GMT.Top.
Project member : Ji-Hoon Park
The recent advances of the CMOS RF technology paved a way to commercially viable wireless communication systems working at multi-Gbps rate. However, a design of baseband circuits for this high-speed system is facing unique challenges. Firstly, (1) minimizing the power consumption is critical especially for mobile devices because the power is proportional to the data rate. Also, (2) as the symbol rate goes up, the propagation channel shows larger delay spread, which makes it harder to equalize the channel. (3) Finally, the recovery of frequency and timing errors between a transmitter and a receiver became challenging problems.
To build a system with reduced power consumption while achieving a performance target, in addition to (1) finding power-efficient architectures and algorithms for the equalization and synchronization, we investigate (2) the power-optimal partition between the analog and digital circuits, and (3) the dynamic reconfiguration of receiver parameters. Specifically, we found an analytic expression of the receiver performance given an impulse response of the propagation channel and tried to find an optimal parameters of the mixed-signal equalizer, so that we can adjust the structure according to the channel conditions and characteristics of the signal. Also, we are working on the channel estimation and synchronization circuit structures, which can achieve its target performance with minimum power consumption.
The goal of this research is to develop a mixed-signal baseband chip to demonstrate the feasibility of this methodology and the architecture.
Sigma-Delta Receiver
Last modified on 2008-09-19 23:06:37 GMT.Top.
Project Member : Renaldi Winoto
The goal of this research is to develop and implement an RF receiver architecture that are amenable to integration in standard digital CMOS process. Specifically, in this project, our focus will be in processing an RF signal using a discrete time ΣΔ modulator. The RF signal is first downcoverted using a current-commutating mixer with a single capacitor as the output load. This capacitor forms the first stage of a two stage passive switched capacitor filter that makes up the ΣΔ modulator loop filter. The switched-capacitor filter is run at radio frequencies which gives rise to a large oversampling ratio. Availability of very good switches is one of the advantages of scaling, as for a given on-resistance; the parasitic capacitance of MOS switch becomes increasingly smaller.
This receiver architecture also provides a very good platform to implement an interference cancellation scheme. First, the receiver actually captures the entire signal up to the sampling frequency, along with the desired RF signal. This means that large, potentially blocking signals are also available at the digital output, although with compromised signal-to-noise ratio. Furthermore, by default the ΣΔ modulator has a feedback path which can be placed very close to the antenna. A digital signal processor can then be used to synthesize a cancelling signal for large interferers based on the receiver digital output. This scheme would significantly reduce the dynamic-range requirement needed for the receiver.
LMS Calibrated Pipeline ADC
Last modified on 2008-10-03 18:41:55 GMT.Top.
