VLSI Technology Exploration
Robust SRAM Design in Deeply Scaled CMOS – Robust Design and Optimization of Deeply Scaled SRAM
Last modified on 2008-12-05 18:17:55 GMT.Top.
Project Member : Zheng Guo
Continued increase in the process variability is perceived to be a major challenge to future technology scaling. These effects are most pronounced minimum-geometry devices used in SRAM cells and seriously limit the scalability of SRAM circuits beyond the 65nm node. Recent advances in robust optimization can provide an efficient framework for optimizing memory under uncertainty. Using this framework, the design of memory will be expressed as a robust geometric program (GP). We have been given an opportunity for a 45nm shuttle with ST Micro. We are designing a large (~1Mb) SRAM test-chip (right) to investigate the effects of variations on SRAM functionality at the 45nm and beyond. In particular, we wish to investigate and measure systematic and random variations in large SRAM arrays and correlate that with measured single device as well as single cell (test structure) variations. In addition, we also hope to use the test-chip to help us extract the parameter variations in 45nm SRAM to fine tune the probabilistic models in this optimization framework.
Detection and Compensation of SRAM Variations in Deeply Scaled CMOS
Last modified on 2008-09-19 23:07:30 GMT.Top.
Project Member : Lauren Jones, Zheng Guo, Seng-Oon Toh, Jason Tsai
As transistor dimensions continue to scale into the deep submicron regime, process variability is significantly impacting yield and performance, threatening future scaling. The impact of this variation on static random access memory (SRAM) is of particular interest, due to the large percentage of die area dominated by memory cells. With cache memories consisting of millions of cells, functionality is dependent on up to six standard deviations of margin to variation. Fluctuations in transistor parameters such as threshold voltage (VTH), gate length and effective width shift read and write margins and degrade cell stability. While new processing effects attempt to compensate for growing variations, their high cost motivates circuit based solutions for continued scaling.
Recent studies in 45nm technology have shown systematic SRAM variation in mean read and write margins between alternating columns and rows. These studies suggest that layout variations due to processing effects cause structures that are physically mirrored across an axis to have different DC characteristics. It is likely that future scaling will increase this deviation. This presents a new challenge in variability compensation of SRAM arrays. We are exploring new compensation techniques that can adapt to variations dynamically and that address asymmetries in read and write margins within memory arrays. Test structures will be realized in a 45nm CMOS process.
